With increasing demands for embedded memory type circuits, mixed-signal circuits, and system on chip (SOC) IC design, it has become necessary to form multiple transistor structures for a semiconductor device IC. For example, transistors with different structures and functions typically operate under different current and voltage parameters requiring different semiconductor doping widths and depths for the various transistors. For example, the width of the LDD region is typically controlled by the width of spacers formed adjacent to a semiconductor gate structure to act as a mask before or following one or more semiconductor substrate doping processes, for example ion implantation, to form regions of differing doping concentrations, for example source/drain (S/D) regions adjacent the LDD regions. The width of the sidewall spacer formed adjacent a gate structure is an important variable in defining the width of the doping regions and consequently defining the particular transistor design performance including threshold operating voltages and currents.
Although methods have been proposed in the prior art for forming multiple width sidewall spacers, the methods generally require an excessive number of photoresist patterning processes and etching processes and/or deposition processes as well as present the possibility of etching damage to the source and drain areas.
Thus, there is a need in the semiconductor device manufacturing art for an improved method for forming sidewall spacers of multiple widths while avoiding etching damage to the source and drain areas.
It is therefore an object of the invention to provide an improved method for forming sidewall spacers of multiple widths while avoiding etching damage to the source and drain areas in addition to overcoming other shortcomings and deficiencies of the prior art.
A principle object of the present invention is to provide a process that allows the formation of spacers with different widths.
Another object of the present invention is to provide a method that includes at least N spacer dielectric layers to produce N spacer widths.